There is an increasing demand for miniaturization in the integrated circuits industry. This demand has led to an ever constant reduction in separation between conductive lines (e.g., metal lines) in order to reduce integrated circuit size and/or increase density. The reduced spacing between the conductive lines has the undesirable effect of increasing the capacitance of whatever material lies between the conductive lines which may give rise to an undesirable phenomenon known as capacitive crosstalk.
In the past, overall integrated circuit (IC) performance depended primarily on device properties, however, this is no longer the case. Parasitic resistance, capacitance and inductance associated with interconnections and contacts of an IC are beginning to become increasingly significant factors in IC performance. In current IC technology, the speed limiting factor is no longer device delay, but the resistive-capacitive (RC) delays associated with the conductive interconnections of the IC (e.g., metal lines).
Conventional ICs typically employ an interconnect structure wherein a first conductive line is adjacent a second conductive line. If the crosstalk or capacitance between the first conductive line and the second conductive line is high, then the voltage on the first conductive line alters or affects the voltage on the second conductive line. This alteration in voltage may result in the IC being inoperable as a result of misinterpreting logic zeros, logic ones and voltage levels, and consequently incorrectly processing binary and/or analog information.
An exemplary semiconductor structure is illustrated in prior art FIG. 1. Prior art FIG. 1 illustrates a typical n-channel MOS transistor 10 between LOCOS-type isolation regions 12. The MOS transistor 10 includes source and drain regions 14 and 16 separated by a channel 18 in a substrate 20. A gate oxide 22 and a polysilicon gate 24 are formed on the substrate 20 over the channel 18. Conductive contacts 26a, 26b and 26c such as metal or a silicide are formed for the source 14, gate 24 and drain 16, respectively, and are isolated from one another with an insulating layer 28. The insulating layer 28 is often called an interlayer dielectric because with multi-layer metal semiconductor processes, the dielectric provides electrical insulation between the metal layers. A second level metal 30 is used to make selective contact down to one of the contacts 26b through the interlayer dielectric (ILD) 28.
Dielectric materials such as silicon dioxide are susceptible to ion contamination and moisture penetration. Furthermore, current deposition and polishing techniques have not reached a level where contamination of the ILD is eliminated. Additionally, voids within the ILD may result due to an imperfect fabrication process. Contaminants are undesirable in the ILD because the contaminants may degrade the performance of the ILD and facilitate unwanted capacitive crosstalk (e.g., leakage) between adjacent metal lines. Voids are not desired because the voids weaken the ILD and may lead to the formation of cracks within the ILD which may also give rise to leakage of current between adjacent metal lines.
Because defects in the interlayer dielectric may result in either parametric or functional device failures, it is desirable to test the interlayer dielectric to determine whether an undesirable number of such defects exist. One prior art method of testing an interlayer dielectric is illustrated in prior art FIG. 2, which illustrates two conductive lines 40 and 42 on a substrate 44 covered with an interlayer dielectric 46, wherein the conductive lines 40 and 42 are biased with a voltage source 48. A current meter 50 is placed in series with the voltage source 48 to measure the leakage current between the lines 40 and 42 flowing through the dielectric 46. Since leakage current is typically very small (e.g., in the order of picoamps), special current meters must be used to detect the leakage and thus are extremely expensive. In addition, such tests are difficult in isolating any detected leakage current from extraneous noise which may be detected.
One solution to the above problem of detecting low level leakage current is to substantially increase the voltage bias above the typical operating voltage in order to increase the leakage current to a more easily detectable level. Increasing the bias voltage in the above manner, however, stresses the dielectric 46 which may increase the leakage in the dielectric 46 and may even result in dielectric breakdown and thus a catastrophic device failure. Furthermore, in either prior art test scenario, a leakage current may be detected which indicates that one or more defects exist within the dielectric 46 and may even indicate an amount of such defects, thereby providing a pass/fail type performance indication. The prior art tests, however, provide no information regarding the location of the defects within the dielectric 46 that give rise to the leakage. Consequently, the test results do not provide defect location information and thus cannot be used significantly as a diagnostic tool in dielectric layer process development.
In addition to the above shortcomings in the prior art, detection of such defects (e.g., contaminants and voids) is typically performed at the end of the process line after the IC is substantially complete. However, the in-line fabrication of the IC represents up to 95% of the cost of the ultimate integrated circuit. Thus, it would be desirable to test the IC during fabrication in order to detect defects in the IC early on before additional monies are spent down the line for later fabrication steps.
In view of the above, it would be desirable to have a system and method for in-line detection of defects in the interlayer dielectric of an integrated circuit which provide not only an indication of whether one or more defects exist, but also indicate the location of the defects within the interlayer dielectric.